# Static Timing Analysis

Project : | Timer01
Build Time : | 08/22/13 13:18:05
Device : | CY8C5868AXI-LP035
Temperature : | -40C - 85/125C
Vdda : | 5.50
Vddd : | 5.50
Vio0 : | 5.50
Vio1 : | 5.50
Vio2 : | 5.50
Vio3 : | 5.50
Voltage : | 5.5
Vusb : | 5.50

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
clock_1 | CyMASTER_CLK | 10.000 kHz | 10.000 kHz | 43.165 MHz |
clock_2 | CyMASTER_CLK | 200.000 Hz | 200.000 Hz | N/A |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |
clock_2(routed) | clock_2(routed) | 200.000 Hz | 200.000 Hz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : clock_1 : Positive edge(Required Frequency 10 kHz)
+ Destination Clock : clock_1 : Positive edge(Required Frequency 10 kHz)
Path Delay Requirement : 100000ns(10 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 43.165 MHz | 23.167 | 99976.833 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 3.087
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 46.005 MHz | 21.737 | 99978.263 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 3.087
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 49.111 MHz | 20.362 | 99979.638 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.982
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 50.284 MHz | 19.887 | 99980.113 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 3.087
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 50.661 MHz | 19.739 | 99980.261 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.939
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 54.180 MHz | 18.457 | 99981.543 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 3.087
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 54.618 MHz | 18.309 | 99981.691 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.939
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 58.018 MHz | 17.236 | 99982.764 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 3.136
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 58.541 MHz | 17.082 | 99982.918 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.982
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:rstSts:stsreg\/status_0 | 64.020 MHz | 15.620 | 99984.380 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:status_tc\/main_1 | 3.106
macrocell5 | U(2,4) | 1 | \Timer_1:TimerUDB:status_tc\ | \Timer_1:TimerUDB:status_tc\/main_1 | \Timer_1:TimerUDB:status_tc\/q | 3.350
Route |  | 1 | \Timer_1:TimerUDB:status_tc\ | \Timer_1:TimerUDB:status_tc\/q | \Timer_1:TimerUDB:rstSts:stsreg\/status_0 | 2.314
statusicell1 | U(2,4) | 1 | \Timer_1:TimerUDB:rstSts:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : clock_1 : Positive edge
+ Destination Clock : clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 3.210 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:capture_last\/q | Net_248/main_2 | 3.550 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(2,4) | 1 | \Timer_1:TimerUDB:capture_last\ | \Timer_1:TimerUDB:capture_last\/clock_0 | \Timer_1:TimerUDB:capture_last\/q | 1.250
Route |  | 1 | \Timer_1:TimerUDB:capture_last\ | \Timer_1:TimerUDB:capture_last\/q | Net_248/main_2 | 2.300
macrocell2 | U(2,4) | 1 | Net_248 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Sync_1:genblk1[0]:INST\/out | \Timer_1:TimerUDB:capture_last\/main_0 | 3.603 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
synccell | U(3,4) | 1 | \Sync_1:genblk1[0]:INST\ | \Sync_1:genblk1[0]:INST\/clock | \Sync_1:genblk1[0]:INST\/out | 1.000
Route |  | 1 | Net_223 | \Sync_1:genblk1[0]:INST\/out | \Timer_1:TimerUDB:capture_last\/main_0 | 2.603
macrocell4 | U(2,4) | 1 | \Timer_1:TimerUDB:capture_last\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Sync_1:genblk1[0]:INST\/out | Net_248/main_1 | 3.616 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
synccell | U(3,4) | 1 | \Sync_1:genblk1[0]:INST\ | \Sync_1:genblk1[0]:INST\/clock | \Sync_1:genblk1[0]:INST\/out | 1.000
Route |  | 1 | Net_223 | \Sync_1:genblk1[0]:INST\/out | Net_248/main_1 | 2.616
macrocell2 | U(2,4) | 1 | Net_248 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 5.022 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.982
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 5.176 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 3.136
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_247/main_0 | 5.194 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_247/main_0 | 3.154
macrocell1 | U(2,4) | 1 | Net_247 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_248/main_0 | 5.194 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(2,4) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_248/main_0 | 3.154
macrocell2 | U(2,4) | 1 | Net_248 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 6.209 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.270
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.939
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 6.357 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.270
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 3.087
datapathcell1 | U(3,4) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ clock_1

Source | Destination | Delay (ns)
--- | --- | ---
Net_248/q | P0_0(0)_PAD | 22.853
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(2,4) | 1 | Net_248 | Net_248/clock_0 | Net_248/q | 1.250
Route |  | 1 | Net_248 | Net_248/q | P0_0(0)/pin_input | 6.352
iocell1 | P0[0] | 1 | P0_0(0) | P0_0(0)/pin_input | P0_0(0)/pad_out | 15.251
Route |  | 1 | P0_0(0)_PAD | P0_0(0)/pad_out | P0_0(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000
Net_247/q | P0_1(0)_PAD | 22.561
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell1 | U(2,4) | 1 | Net_247 | Net_247/clock_0 | Net_247/q | 1.250
Route |  | 1 | Net_247 | Net_247/q | P0_1(0)/pin_input | 5.509
iocell2 | P0[1] | 1 | P0_1(0) | P0_1(0)/pin_input | P0_1(0)/pad_out | 15.802
Route |  | 1 | P0_1(0)_PAD | P0_1(0)/pad_out | P0_1(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000