    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv.inc
    GET cydevicerv_trm.inc

; Timer_1_TimerUDB
Timer_1_TimerUDB_rstSts_stsreg__0__MASK EQU 0x01
Timer_1_TimerUDB_rstSts_stsreg__0__POS EQU 0
Timer_1_TimerUDB_rstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
Timer_1_TimerUDB_rstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
Timer_1_TimerUDB_rstSts_stsreg__1__MASK EQU 0x02
Timer_1_TimerUDB_rstSts_stsreg__1__POS EQU 1
Timer_1_TimerUDB_rstSts_stsreg__2__MASK EQU 0x04
Timer_1_TimerUDB_rstSts_stsreg__2__POS EQU 2
Timer_1_TimerUDB_rstSts_stsreg__3__MASK EQU 0x08
Timer_1_TimerUDB_rstSts_stsreg__3__POS EQU 3
Timer_1_TimerUDB_rstSts_stsreg__MASK EQU 0x0F
Timer_1_TimerUDB_rstSts_stsreg__MASK_REG EQU CYREG_B0_UDB03_MSK
Timer_1_TimerUDB_rstSts_stsreg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
Timer_1_TimerUDB_rstSts_stsreg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
Timer_1_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
Timer_1_TimerUDB_rstSts_stsreg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
Timer_1_TimerUDB_rstSts_stsreg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
Timer_1_TimerUDB_rstSts_stsreg__STATUS_REG EQU CYREG_B0_UDB03_ST
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK EQU 0x80
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS EQU 7
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG EQU CYREG_B0_UDB03_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK EQU 0x80
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG EQU CYREG_B0_UDB02_03_A0
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG EQU CYREG_B0_UDB02_03_A1
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG EQU CYREG_B0_UDB02_03_D0
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG EQU CYREG_B0_UDB02_03_D1
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG EQU CYREG_B0_UDB02_03_F0
Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG EQU CYREG_B0_UDB02_03_F1
Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG EQU CYREG_B0_UDB02_A0_A1
Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG EQU CYREG_B0_UDB02_A0
Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG EQU CYREG_B0_UDB02_A1
Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG EQU CYREG_B0_UDB02_D0_D1
Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG EQU CYREG_B0_UDB02_D0
Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG EQU CYREG_B0_UDB02_D1
Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG EQU CYREG_B0_UDB02_F0_F1
Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG EQU CYREG_B0_UDB02_F0
Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG EQU CYREG_B0_UDB02_F1
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG EQU CYREG_B0_UDB03_A0
Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG EQU CYREG_B0_UDB03_A1
Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG EQU CYREG_B0_UDB03_D0
Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG EQU CYREG_B0_UDB03_D1
Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG EQU CYREG_B0_UDB03_F0
Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG EQU CYREG_B0_UDB03_F1
Timer_1_TimerUDB_sT16_timerdp_u1__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
Timer_1_TimerUDB_sT16_timerdp_u1__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL

; scheduler_out
scheduler_out__0__MASK EQU 0x01
scheduler_out__0__PC EQU CYREG_PRT3_PC0
scheduler_out__0__PORT EQU 3
scheduler_out__0__SHIFT EQU 0
scheduler_out__AG EQU CYREG_PRT3_AG
scheduler_out__AMUX EQU CYREG_PRT3_AMUX
scheduler_out__BIE EQU CYREG_PRT3_BIE
scheduler_out__BIT_MASK EQU CYREG_PRT3_BIT_MASK
scheduler_out__BYP EQU CYREG_PRT3_BYP
scheduler_out__CTL EQU CYREG_PRT3_CTL
scheduler_out__DM0 EQU CYREG_PRT3_DM0
scheduler_out__DM1 EQU CYREG_PRT3_DM1
scheduler_out__DM2 EQU CYREG_PRT3_DM2
scheduler_out__DR EQU CYREG_PRT3_DR
scheduler_out__INP_DIS EQU CYREG_PRT3_INP_DIS
scheduler_out__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
scheduler_out__LCD_EN EQU CYREG_PRT3_LCD_EN
scheduler_out__MASK EQU 0x01
scheduler_out__PORT EQU 3
scheduler_out__PRT EQU CYREG_PRT3_PRT
scheduler_out__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
scheduler_out__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
scheduler_out__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
scheduler_out__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
scheduler_out__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
scheduler_out__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
scheduler_out__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
scheduler_out__PS EQU CYREG_PRT3_PS
scheduler_out__SHIFT EQU 0
scheduler_out__SLW EQU CYREG_PRT3_SLW

; LCD_LCDPort
LCD_LCDPort__0__MASK EQU 0x01
LCD_LCDPort__0__PC EQU CYREG_PRT2_PC0
LCD_LCDPort__0__PORT EQU 2
LCD_LCDPort__0__SHIFT EQU 0
LCD_LCDPort__1__MASK EQU 0x02
LCD_LCDPort__1__PC EQU CYREG_PRT2_PC1
LCD_LCDPort__1__PORT EQU 2
LCD_LCDPort__1__SHIFT EQU 1
LCD_LCDPort__2__MASK EQU 0x04
LCD_LCDPort__2__PC EQU CYREG_PRT2_PC2
LCD_LCDPort__2__PORT EQU 2
LCD_LCDPort__2__SHIFT EQU 2
LCD_LCDPort__3__MASK EQU 0x08
LCD_LCDPort__3__PC EQU CYREG_PRT2_PC3
LCD_LCDPort__3__PORT EQU 2
LCD_LCDPort__3__SHIFT EQU 3
LCD_LCDPort__4__MASK EQU 0x10
LCD_LCDPort__4__PC EQU CYREG_PRT2_PC4
LCD_LCDPort__4__PORT EQU 2
LCD_LCDPort__4__SHIFT EQU 4
LCD_LCDPort__5__MASK EQU 0x20
LCD_LCDPort__5__PC EQU CYREG_PRT2_PC5
LCD_LCDPort__5__PORT EQU 2
LCD_LCDPort__5__SHIFT EQU 5
LCD_LCDPort__6__MASK EQU 0x40
LCD_LCDPort__6__PC EQU CYREG_PRT2_PC6
LCD_LCDPort__6__PORT EQU 2
LCD_LCDPort__6__SHIFT EQU 6
LCD_LCDPort__AG EQU CYREG_PRT2_AG
LCD_LCDPort__AMUX EQU CYREG_PRT2_AMUX
LCD_LCDPort__BIE EQU CYREG_PRT2_BIE
LCD_LCDPort__BIT_MASK EQU CYREG_PRT2_BIT_MASK
LCD_LCDPort__BYP EQU CYREG_PRT2_BYP
LCD_LCDPort__CTL EQU CYREG_PRT2_CTL
LCD_LCDPort__DM0 EQU CYREG_PRT2_DM0
LCD_LCDPort__DM1 EQU CYREG_PRT2_DM1
LCD_LCDPort__DM2 EQU CYREG_PRT2_DM2
LCD_LCDPort__DR EQU CYREG_PRT2_DR
LCD_LCDPort__INP_DIS EQU CYREG_PRT2_INP_DIS
LCD_LCDPort__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
LCD_LCDPort__LCD_EN EQU CYREG_PRT2_LCD_EN
LCD_LCDPort__MASK EQU 0x7F
LCD_LCDPort__PORT EQU 2
LCD_LCDPort__PRT EQU CYREG_PRT2_PRT
LCD_LCDPort__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
LCD_LCDPort__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
LCD_LCDPort__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
LCD_LCDPort__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
LCD_LCDPort__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
LCD_LCDPort__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
LCD_LCDPort__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
LCD_LCDPort__PS EQU CYREG_PRT2_PS
LCD_LCDPort__SHIFT EQU 0
LCD_LCDPort__SLW EQU CYREG_PRT2_SLW

; TimerISR
TimerISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
TimerISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
TimerISR__INTC_MASK EQU 0x01
TimerISR__INTC_NUMBER EQU 0
TimerISR__INTC_PRIOR_NUM EQU 7
TimerISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
TimerISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
TimerISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; clock_1
clock_1__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
clock_1__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
clock_1__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
clock_1__CFG2_SRC_SEL_MASK EQU 0x07
clock_1__INDEX EQU 0x00
clock_1__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
clock_1__PM_ACT_MSK EQU 0x01
clock_1__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
clock_1__PM_STBY_MSK EQU 0x01

; clock_2
clock_2__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
clock_2__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
clock_2__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
clock_2__CFG2_SRC_SEL_MASK EQU 0x07
clock_2__INDEX EQU 0x01
clock_2__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
clock_2__PM_ACT_MSK EQU 0x02
clock_2__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
clock_2__PM_STBY_MSK EQU 0x02

; P0_0
P0_0__0__MASK EQU 0x01
P0_0__0__PC EQU CYREG_PRT0_PC0
P0_0__0__PORT EQU 0
P0_0__0__SHIFT EQU 0
P0_0__AG EQU CYREG_PRT0_AG
P0_0__AMUX EQU CYREG_PRT0_AMUX
P0_0__BIE EQU CYREG_PRT0_BIE
P0_0__BIT_MASK EQU CYREG_PRT0_BIT_MASK
P0_0__BYP EQU CYREG_PRT0_BYP
P0_0__CTL EQU CYREG_PRT0_CTL
P0_0__DM0 EQU CYREG_PRT0_DM0
P0_0__DM1 EQU CYREG_PRT0_DM1
P0_0__DM2 EQU CYREG_PRT0_DM2
P0_0__DR EQU CYREG_PRT0_DR
P0_0__INP_DIS EQU CYREG_PRT0_INP_DIS
P0_0__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
P0_0__LCD_EN EQU CYREG_PRT0_LCD_EN
P0_0__MASK EQU 0x01
P0_0__PORT EQU 0
P0_0__PRT EQU CYREG_PRT0_PRT
P0_0__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
P0_0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
P0_0__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
P0_0__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
P0_0__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
P0_0__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
P0_0__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
P0_0__PS EQU CYREG_PRT0_PS
P0_0__SHIFT EQU 0
P0_0__SLW EQU CYREG_PRT0_SLW

; P0_1
P0_1__0__MASK EQU 0x02
P0_1__0__PC EQU CYREG_PRT0_PC1
P0_1__0__PORT EQU 0
P0_1__0__SHIFT EQU 1
P0_1__AG EQU CYREG_PRT0_AG
P0_1__AMUX EQU CYREG_PRT0_AMUX
P0_1__BIE EQU CYREG_PRT0_BIE
P0_1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
P0_1__BYP EQU CYREG_PRT0_BYP
P0_1__CTL EQU CYREG_PRT0_CTL
P0_1__DM0 EQU CYREG_PRT0_DM0
P0_1__DM1 EQU CYREG_PRT0_DM1
P0_1__DM2 EQU CYREG_PRT0_DM2
P0_1__DR EQU CYREG_PRT0_DR
P0_1__INP_DIS EQU CYREG_PRT0_INP_DIS
P0_1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
P0_1__LCD_EN EQU CYREG_PRT0_LCD_EN
P0_1__MASK EQU 0x02
P0_1__PORT EQU 0
P0_1__PRT EQU CYREG_PRT0_PRT
P0_1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
P0_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
P0_1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
P0_1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
P0_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
P0_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
P0_1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
P0_1__PS EQU CYREG_PRT0_PS
P0_1__SHIFT EQU 1
P0_1__SLW EQU CYREG_PRT0_SLW

; Miscellaneous
; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_MEMBER_5B EQU 4
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 4
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 3
CYDEV_CHIP_DIE_PSOC4A EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E123069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 2
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 0
CYDEV_INTR_RISING EQU 0x00000001
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x4000
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA_MV EQU 5500
CYDEV_VDDD_MV EQU 5500
CYDEV_VDDIO0_MV EQU 5500
CYDEV_VDDIO1_MV EQU 5500
CYDEV_VDDIO2_MV EQU 5500
CYDEV_VDDIO3_MV EQU 5500
CYDEV_VIO0_MV EQU 5500
CYDEV_VIO1_MV EQU 5500
CYDEV_VIO2_MV EQU 5500
CYDEV_VIO3_MV EQU 5500
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
