Static Timing Analysis

Project : code_performance
Build Time : 07/01/13 15:48:52
Device : CY8C5568AXI-060
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 30.088 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 30.088 MHz 33.236 8.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 31.441 MHz 31.806 9.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 32.921 MHz 30.376 11.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 33.203 MHz 30.118 11.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.868
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 33.416 MHz 29.926 11.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 34.547 MHz 28.946 12.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.850
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 34.858 MHz 28.688 12.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.868
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 35.093 MHz 28.496 13.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 36.686 MHz 27.258 14.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.868
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 36.906 MHz 27.096 14.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 3.096
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_1 5.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_1 2.973
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 5.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 3.096
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_29/main_0 5.156
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_29/main_0 3.116
macrocell1 U(1,2) 1 Net_29 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_1 5.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_1 3.868
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_1 6.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_1 3.983
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000