Static Timing Analysis

Project : Timer01
Build Time : 07/03/13 11:58:52
Device : CY8C5568AXI-060
Temperature : -40C - 85/125C
Vdda : 5.50
Vddd : 5.50
Vio0 : 5.50
Vio1 : 5.50
Vio2 : 5.50
Vio3 : 5.50
Voltage : 5.5
Vusb : 5.50
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
clock_1 CyMASTER_CLK 10.000 kHz 10.000 kHz 42.629 MHz
clock_2 CyMASTER_CLK 200.000  Hz 200.000  Hz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 48.137 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
clock_2(routed) clock_2(routed) 200.000  Hz 200.000  Hz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 48.137 MHz 20.774 20.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.394
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 48.842 MHz 20.474 21.193
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.094
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 56.587 MHz 17.672 23.995
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.572
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 57.162 MHz 17.494 24.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.394
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_1 58.153 MHz 17.196 24.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.096
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 58.160 MHz 17.194 24.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.094
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/f0_load 69.585 MHz 14.371 27.296
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:capt_fifo_load\/main_0 3.409
macrocell3 U(0,5) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_0 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/f0_load 3.102
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 1.930
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/f0_load 70.215 MHz 14.242 27.425
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:capt_fifo_load\/main_0 3.409
macrocell3 U(0,5) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_0 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/f0_load 2.973
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 1.930
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 71.342 MHz 14.017 27.650
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:capt_fifo_load\/main_0 3.409
macrocell3 U(0,5) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_0 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 3.108
statusicell1 U(1,5) 1 \Timer_1:TimerUDB:nrstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/f0_load 71.674 MHz 13.952 27.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:capt_fifo_load\/main_1 2.992
macrocell6 U(0,4) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_1 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT16:timerdp:u1\/f0_load 3.100
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 1.930
Clock Skew 0.000
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 42.629 MHz 23.458 99976.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.378
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 43.405 MHz 23.039 99976.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/clock \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.959
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 45.397 MHz 22.028 99977.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.378
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 46.277 MHz 21.609 99978.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/clock \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.959
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 49.559 MHz 20.178 99979.822
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.378
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 49.561 MHz 20.177 99979.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.377
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_0 50.226 MHz 19.910 99980.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/clock \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.110
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 50.610 MHz 19.759 99980.241
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/clock \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/z0 \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0i \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.959
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 53.339 MHz 18.748 99981.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.378
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 53.342 MHz 18.747 99981.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.377
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 5.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.094
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.096
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 5.434
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.394
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_247/main_0 5.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_247/main_0 3.409
macrocell1 U(0,5) 1 Net_247 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.572
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_293/main_0 5.621
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 Net_293/main_0 3.581
macrocell2 U(0,5) 1 Net_293 HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:nrstSts:stsreg\/status_0 8.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:status_tc\/main_0 2.992
macrocell7 U(0,4) 1 \Timer_2:TimerUDB:status_tc\ \Timer_2:TimerUDB:status_tc\/main_0 \Timer_2:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_2:TimerUDB:status_tc\ \Timer_2:TimerUDB:status_tc\/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_0 2.325
statusicell2 U(0,4) 1 \Timer_2:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:nrstSts:stsreg\/status_0 9.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:status_tc\/main_0 3.594
macrocell5 U(1,5) 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/main_0 \Timer_1:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_1:TimerUDB:status_tc\ \Timer_1:TimerUDB:status_tc\/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_0 2.311
statusicell1 U(1,5) 1 \Timer_1:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 9.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_2:TimerUDB:control_7\ \Timer_2:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_2:TimerUDB:capt_fifo_load\/main_1 2.992
macrocell6 U(0,4) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_1 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 3.105
statusicell2 U(0,4) 1 \Timer_2:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 9.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:capt_fifo_load\/main_0 3.409
macrocell3 U(0,5) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_0 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 3.108
statusicell1 U(1,5) 1 \Timer_1:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ \Timer_2:TimerUDB:sT16:timerdp:u0\/clock \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out Net_293/main_1 3.631
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_269 \Sync_1:genblk1[0]:INST\/out Net_293/main_1 2.631
macrocell2 U(0,5) 1 Net_293 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:capture_last\/q Net_293/main_2 4.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,4) 1 \Timer_1:TimerUDB:capture_last\ \Timer_1:TimerUDB:capture_last\/clock_0 \Timer_1:TimerUDB:capture_last\/q 1.250
Route 1 \Timer_1:TimerUDB:capture_last\ \Timer_1:TimerUDB:capture_last\/q Net_293/main_2 3.370
macrocell2 U(0,5) 1 Net_293 HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out \Timer_1:TimerUDB:capture_last\/main_0 4.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_269 \Sync_1:genblk1[0]:INST\/out \Timer_1:TimerUDB:capture_last\/main_0 3.731
macrocell4 U(0,4) 1 \Timer_1:TimerUDB:capture_last\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.229
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/clock \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.959
datapathcell3 U(1,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb Net_247/main_1 6.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb Net_247/main_1 3.108
macrocell1 U(0,5) 1 Net_247 HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/clock \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ \Timer_2:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_2:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.110
datapathcell4 U(0,4) 1 \Timer_2:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.377
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/clock \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.378
datapathcell1 U(0,5) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ clock_1
Source Destination Delay (ns)
Net_293/q P0_0(0)_PAD 25.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,5) 1 Net_293 Net_293/clock_0 Net_293/q 1.250
Route 1 Net_293 Net_293/q P0_0(0)/pin_input 5.450
iocell1 P0[0] 1 P0_0(0) P0_0(0)/pin_input P0_0(0)/pad_out 19.103
Route 1 P0_0(0)_PAD P0_0(0)/pad_out P0_0(0)_PAD 0.000
Clock Clock path delay 0.000
Net_247/q P0_1(0)_PAD 25.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,5) 1 Net_247 Net_247/clock_0 Net_247/q 1.250
Route 1 Net_247 Net_247/q P0_1(0)/pin_input 5.446
iocell2 P0[1] 1 P0_1(0) P0_1(0)/pin_input P0_1(0)/pad_out 18.846
Route 1 P0_1(0)_PAD P0_1(0)/pad_out P0_1(0)_PAD 0.000
Clock Clock path delay 0.000