Static Timing Analysis

Project : Demo
Build Time : 04/04/15 14:10:48
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 48.000 MHz 48.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 48.000 MHz 48.000 MHz N/A
ADC_DelSig_theACLK(fixed-function) ADC_DelSig_theACLK(fixed-function) 3.000 MHz 3.000 MHz N/A
ADC_SAR_1_theACLK(fixed-function) ADC_SAR_1_theACLK(fixed-function) 1.778 MHz 1.778 MHz N/A
ADC_SAR_2_theACLK(fixed-function) ADC_SAR_2_theACLK(fixed-function) 1.778 MHz 1.778 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CapSense_IntClock CyMASTER_CLK 12.000 MHz 12.000 MHz 37.390 MHz
ADC_DelSig_theACLK CyMASTER_CLK 3.000 MHz 3.000 MHz N/A
ADC_SAR_2_theACLK CyMASTER_CLK 1.778 MHz 1.778 MHz N/A
ADC_SAR_1_theACLK CyMASTER_CLK 1.778 MHz 1.778 MHz N/A
Timer_Clock_1MHz CyMASTER_CLK 1.000 MHz 1.000 MHz 29.977 MHz
UART_IntClock CyMASTER_CLK 461.538 kHz 461.538 kHz 41.022 MHz
PWM_2_Clock CyMASTER_CLK 25.000 kHz 25.000 kHz N/A
PWM_1_Clock CyMASTER_CLK 25.000 kHz 25.000 kHz N/A
Debouncer_Clock CyMASTER_CLK 10.000 kHz 10.000 kHz 130.907 MHz
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 64.029 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
PWM_1_Clock(fixed-function) PWM_1_Clock(fixed-function) 25.000 kHz 25.000 kHz N/A
PWM_2_Clock(fixed-function) PWM_2_Clock(fixed-function) 25.000 kHz 25.000 kHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CapSense:MeasureCH0:genblk1:SyncCMPR\/out \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 37.390 MHz 26.745 56.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,2) 1 \CapSense:MeasureCH0:genblk1:SyncCMPR\ \CapSense:MeasureCH0:genblk1:SyncCMPR\/clock \CapSense:MeasureCH0:genblk1:SyncCMPR\/out 1.480
Route 1 \CapSense:IdacCH0:Net_123\ \CapSense:MeasureCH0:genblk1:SyncCMPR\/out \CapSense:MeasureCH0:cs_addr_cnt_0\/main_0 6.733
macrocell11 U(1,5) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_0 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 3.652
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Counter:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 38.469 MHz 25.995 57.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ \CapSense:MeasureCH0:UDB:Counter:u0\/clock \CapSense:MeasureCH0:UDB:Counter:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zc1\ \CapSense:MeasureCH0:UDB:Counter:u0\/z1_comb \CapSense:MeasureCH0:cs_addr_cnt_0\/main_3 3.643
macrocell11 U(1,5) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_3 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 3.652
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 39.208 MHz 25.505 57.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 4.463
macrocell13 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 39.219 MHz 25.498 57.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 4.456
macrocell12 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 \CapSense:MeasureCH0:cs_addr_cnt_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 39.262 MHz 25.470 57.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 4.458
macrocell13 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 39.280 MHz 25.458 57.875
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 4.446
macrocell12 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:genblk1:SyncCMPR\/out \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 39.640 MHz 25.227 58.106
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,2) 1 \CapSense:MeasureCH0:genblk1:SyncCMPR\ \CapSense:MeasureCH0:genblk1:SyncCMPR\/clock \CapSense:MeasureCH0:genblk1:SyncCMPR\/out 1.480
Route 1 \CapSense:IdacCH0:Net_123\ \CapSense:MeasureCH0:genblk1:SyncCMPR\/out \CapSense:MeasureCH0:cs_addr_cnt_2\/main_0 6.555
macrocell13 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_0 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 40.011 MHz 24.993 58.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 2.611
macrocell11 U(1,5) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 3.652
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 40.075 MHz 24.953 58.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 2.601
macrocell11 U(1,5) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 3.652
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 41.230 MHz 24.254 59.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,5) 1 \CapSense:MeasureCH0:wndState_2\ \CapSense:MeasureCH0:wndState_2\/clock_0 \CapSense:MeasureCH0:wndState_2\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_2\ \CapSense:MeasureCH0:wndState_2\/q \CapSense:MeasureCH0:cs_addr_cnt_2\/main_3 5.812
macrocell13 U(1,3) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_3 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.312
datapathcell2 U(1,3) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
P6_1(0)_SYNC/out \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 137.043 MHz 7.297 13.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,1) 1 P6_1(0)_SYNC P6_1(0)_SYNC/clock P6_1(0)_SYNC/out 1.480
Route 1 Net_158_SYNCOUT P6_1(0)_SYNC/out \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 2.307
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Skew 0.000
P15_5(0)_SYNC/out \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 137.287 MHz 7.284 13.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,1) 1 P15_5(0)_SYNC P15_5(0)_SYNC/clock P15_5(0)_SYNC/out 1.480
Route 1 Net_161_SYNCOUT P15_5(0)_SYNC/out \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 2.294
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
P6_6(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 64.029 MHz 15.618 5.215
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 3.257
macrocell36 U(1,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.321
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 120.846 MHz 8.275 12.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.285
macrocell37 U(0,4) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 120.846 MHz 8.275 12.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.285
macrocell38 U(0,4) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 120.977 MHz 8.266 12.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.276
macrocell41 U(0,4) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 121.256 MHz 8.247 12.586
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 3.257
macrocell29 U(1,4) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 121.256 MHz 8.247 12.586
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 3.257
macrocell30 U(1,4) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_last\/main_0 121.462 MHz 8.233 12.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.480
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_last\/main_0 3.243
macrocell34 U(1,4) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_59/main_0 130.907 MHz 7.639 99992.361
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_59/main_0 2.879
macrocell5 U(2,0) 1 Net_59 SETUP 3.510
Clock Skew 0.000
\SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 131.199 MHz 7.622 99992.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.862
macrocell24 U(2,0) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ SETUP 3.510
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_64/main_0 132.135 MHz 7.568 99992.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_64/main_0 2.808
macrocell7 U(2,1) 1 Net_64 SETUP 3.510
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 132.223 MHz 7.563 99992.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.803
macrocell26 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ SETUP 3.510
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_64/main_1 141.784 MHz 7.053 99992.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_64/main_1 2.293
macrocell7 U(2,1) 1 Net_64 SETUP 3.510
Clock Skew 0.000
\SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_59/main_1 142.755 MHz 7.005 99992.995
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,0) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_59/main_1 2.245
macrocell5 U(2,0) 1 Net_59 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 29.977 MHz 33.359 966.641
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 31.319 MHz 31.929 968.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 32.788 MHz 30.499 969.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 33.276 MHz 30.052 969.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.802
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 33.279 MHz 30.049 969.951
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 34.401 MHz 29.069 970.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 3.850
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 34.938 MHz 28.622 971.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.802
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 34.942 MHz 28.619 971.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 36.776 MHz 27.192 972.808
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.802
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 36.780 MHz 27.189 972.811
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.799
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 41.022 MHz 24.377 2142.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(1,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 5.965
macrocell28 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell10 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.373 MHz 23.600 2143.067
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(0,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 5.188
macrocell28 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell10 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.572 MHz 21.472 2145.195
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell48 U(1,2) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_2 3.060
macrocell28 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell10 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.832 MHz 21.353 2145.314
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(0,2) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:counter_load_not\/main_3 2.941
macrocell28 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell10 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 47.615 MHz 21.002 2145.665
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART:BUART:tx_bitclk_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:tx_bitclk_enable_pre\/main_0 3.390
macrocell45 U(0,1) 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/main_0 \UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/q \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.292
datapathcell9 U(0,1) 1 \UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 60.071 MHz 16.647 2150.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell9 U(0,1) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_2 4.120
macrocell49 U(0,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_2 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.327
statusicell3 U(0,1) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 61.629 MHz 16.226 2150.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,4) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 4.095
macrocell36 U(1,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.321
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 64.696 MHz 15.457 2151.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.926
macrocell42 U(0,3) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 2.331
statusicell2 U(0,3) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 64.914 MHz 15.405 2151.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,4) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_1 3.274
macrocell36 U(1,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.321
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 65.841 MHz 15.188 2151.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(0,4) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.050
macrocell33 U(0,4) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.318
count7cell U(0,4) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\CapSense:Net_1603\/q \CapSense:MeasureCH0:wndState_0\/main_4 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,5) 1 \CapSense:Net_1603\ \CapSense:Net_1603\/clock_0 \CapSense:Net_1603\/q 1.250
Route 1 \CapSense:Net_1603\ \CapSense:Net_1603\/q \CapSense:MeasureCH0:wndState_0\/main_4 2.297
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ HOLD 0.000
Clock Skew 0.000
\CapSense:Net_1603\/q \CapSense:MeasureCH0:wndState_2\/main_5 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,5) 1 \CapSense:Net_1603\ \CapSense:Net_1603\/clock_0 \CapSense:Net_1603\/q 1.250
Route 1 \CapSense:Net_1603\ \CapSense:Net_1603\/q \CapSense:MeasureCH0:wndState_2\/main_5 2.297
macrocell19 U(1,5) 1 \CapSense:MeasureCH0:wndState_2\ HOLD 0.000
Clock Skew 0.000
\CapSense:Net_1603\/q \CapSense:Net_1603\/main_6 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,5) 1 \CapSense:Net_1603\ \CapSense:Net_1603\/clock_0 \CapSense:Net_1603\/q 1.250
macrocell20 U(1,5) 1 \CapSense:Net_1603\ \CapSense:Net_1603\/q \CapSense:Net_1603\/main_6 2.297
macrocell20 U(1,5) 1 \CapSense:Net_1603\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_1\/q \CapSense:MeasureCH0:wndState_1\/main_5 3.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,3) 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/clock_0 \CapSense:MeasureCH0:wndState_1\/q 1.250
macrocell18 U(1,3) 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/q \CapSense:MeasureCH0:wndState_1\/main_5 2.310
macrocell18 U(1,3) 1 \CapSense:MeasureCH0:wndState_1\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_0\/q \CapSense:MeasureCH0:wndState_0\/main_3 3.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/clock_0 \CapSense:MeasureCH0:wndState_0\/q 1.250
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/q \CapSense:MeasureCH0:wndState_0\/main_3 2.606
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_0\/q \CapSense:MeasureCH0:wndState_2\/main_4 3.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/clock_0 \CapSense:MeasureCH0:wndState_0\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/q \CapSense:MeasureCH0:wndState_2\/main_4 2.606
macrocell19 U(1,5) 1 \CapSense:MeasureCH0:wndState_2\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_0\/q \CapSense:Net_1603\/main_5 3.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/clock_0 \CapSense:MeasureCH0:wndState_0\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_0\ \CapSense:MeasureCH0:wndState_0\/q \CapSense:Net_1603\/main_5 2.606
macrocell20 U(1,5) 1 \CapSense:Net_1603\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:cstate_2\/q \CapSense:MeasureCH0:wndState_0\/main_6 4.022
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,5) 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/clock_0 \CapSense:ClockGen:cstate_2\/q 1.250
Route 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/q \CapSense:MeasureCH0:wndState_0\/main_6 2.772
macrocell17 U(1,5) 1 \CapSense:MeasureCH0:wndState_0\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:cstate_2\/q \CapSense:Net_1603\/main_8 4.022
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,5) 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/clock_0 \CapSense:ClockGen:cstate_2\/q 1.250
Route 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/q \CapSense:Net_1603\/main_8 2.772
macrocell20 U(1,5) 1 \CapSense:Net_1603\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:cstate_2\/q \CapSense:ClockGen:cstate_2\/main_4 4.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,5) 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/clock_0 \CapSense:ClockGen:cstate_2\/q 1.250
macrocell9 U(1,5) 1 \CapSense:ClockGen:cstate_2\ \CapSense:ClockGen:cstate_2\/q \CapSense:ClockGen:cstate_2\/main_4 2.776
macrocell9 U(1,5) 1 \CapSense:ClockGen:cstate_2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
P15_5(0)_SYNC/out \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 3.294
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,1) 1 P15_5(0)_SYNC P15_5(0)_SYNC/clock P15_5(0)_SYNC/out 1.000
Route 1 Net_161_SYNCOUT P15_5(0)_SYNC/out \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 2.294
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ HOLD 0.000
Clock Skew 0.000
P6_1(0)_SYNC/out \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 3.307
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,1) 1 P6_1(0)_SYNC P6_1(0)_SYNC/clock P6_1(0)_SYNC/out 1.000
Route 1 Net_158_SYNCOUT P6_1(0)_SYNC/out \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/main_0 2.307
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
P6_6(0)_SYNC/out \UART:BUART:rx_last\/main_0 4.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_last\/main_0 3.243
macrocell34 U(1,4) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 4.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 3.257
macrocell29 U(1,4) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 4.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 3.257
macrocell30 U(1,4) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 4.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.276
macrocell41 U(0,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 4.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.285
macrocell37 U(0,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 4.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.285
macrocell38 U(0,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
P6_6(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 9.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,4) 1 P6_6(0)_SYNC P6_6(0)_SYNC/clock P6_6(0)_SYNC/out 1.000
Route 1 Net_11_SYNCOUT P6_6(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 3.257
macrocell36 U(1,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.321
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_59/main_1 3.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,0) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_59/main_1 2.245
macrocell5 U(2,0) 1 Net_59 HOLD 0.000
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_64/main_1 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/q Net_64/main_1 2.293
macrocell7 U(2,1) 1 Net_64 HOLD 0.000
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 4.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.803
macrocell26 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_1\ HOLD 0.000
Clock Skew 0.000
\SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_64/main_0 4.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW3_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_64/main_0 2.808
macrocell7 U(2,1) 1 Net_64 HOLD 0.000
Clock Skew 0.000
\SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 4.112
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\/main_0 2.862
macrocell24 U(2,0) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_1\ HOLD 0.000
Clock Skew 0.000
\SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_59/main_0 4.129
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,1) 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/clock_0 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\ \SW2_Debouncer:DEBOUNCER[0]:d_sync_0\/q Net_59/main_0 2.879
macrocell5 U(2,0) 1 Net_59 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 3.210
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_1 5.180
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1MHz:TimerUDB:control_7\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/cs_addr_1 3.140
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_1 5.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1MHz:TimerUDB:control_7\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/cs_addr_1 3.142
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/ci \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/cs_addr_0 5.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/cs_addr_0 2.581
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/cs_addr_0 5.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u3\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/clock \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_1MHz:TimerUDB:per_zero\ \Timer_1MHz:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/cs_addr_0 2.584
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/cs_addr_1 6.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,0) 1 \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1MHz:TimerUDB:control_7\ \Timer_1MHz:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\/cs_addr_1 4.553
datapathcell6 U(3,1) 1 \Timer_1MHz:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,4) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.903
statusicell2 U(0,3) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_8 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(1,4) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_8 2.293
macrocell38 U(0,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell51 U(0,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.302
macrocell51 U(0,2) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 2.595
macrocell35 U(0,4) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_0\/main_3 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_0\/main_3 2.595
macrocell37 U(0,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 2.595
macrocell38 U(0,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 2.595
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 2.595
macrocell40 U(0,4) 1 \UART:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_status_3\/main_3 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_status_3\/main_3 2.595
macrocell41 U(0,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 3.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,4) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 2.613
datapathcell8 U(0,4) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LED3_Control:LED_Reg:Sync:ctrl_reg\/control_0 P6_2(0)_PAD 31.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,2) 1 \LED3_Control:LED_Reg:Sync:ctrl_reg\ \LED3_Control:LED_Reg:Sync:ctrl_reg\/busclk \LED3_Control:LED_Reg:Sync:ctrl_reg\/control_0 2.580
Route 1 \LED3_Control:Net_169_0\ \LED3_Control:LED_Reg:Sync:ctrl_reg\/control_0 Net_50/main_4 2.324
macrocell4 U(0,2) 1 Net_50 Net_50/main_4 Net_50/q 3.350
Route 1 Net_50 Net_50/q P6_2(0)/pin_input 7.429
iocell13 P6[2] 1 P6_2(0) P6_2(0)/pin_input P6_2(0)/pad_out 15.746
Route 1 P6_2(0)_PAD P6_2(0)/pad_out P6_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED4_Control:LED_Reg:Sync:ctrl_reg\/control_0 P6_3(0)_PAD 30.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,1) 1 \LED4_Control:LED_Reg:Sync:ctrl_reg\ \LED4_Control:LED_Reg:Sync:ctrl_reg\/busclk \LED4_Control:LED_Reg:Sync:ctrl_reg\/control_0 2.580
Route 1 \LED4_Control:Net_169_0\ \LED4_Control:LED_Reg:Sync:ctrl_reg\/control_0 Net_43/main_4 2.321
macrocell3 U(0,1) 1 Net_43 Net_43/main_4 Net_43/q 3.350
Route 1 Net_43 Net_43/q P6_3(0)/pin_input 7.501
iocell14 P6[3] 1 P6_3(0) P6_3(0)/pin_input P6_3(0)/pad_out 15.011
Route 1 P6_3(0)_PAD P6_3(0)/pad_out P6_3(0)_PAD 0.000
Clock Clock path delay 0.000
+ PWM_1_Clock(fixed-function)
Source Destination Delay (ns)
\PWM_1:PWMHW\/cmp P6_2(0)_PAD 35.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,0) 1 \PWM_1:PWMHW\ \PWM_1:PWMHW\/clock \PWM_1:PWMHW\/cmp 1.000
Route 1 Net_187 \PWM_1:PWMHW\/cmp Net_50/main_1 8.104
macrocell4 U(0,2) 1 Net_50 Net_50/main_1 Net_50/q 3.350
Route 1 Net_50 Net_50/q P6_2(0)/pin_input 7.429
iocell13 P6[2] 1 P6_2(0) P6_2(0)/pin_input P6_2(0)/pad_out 15.746
Route 1 P6_2(0)_PAD P6_2(0)/pad_out P6_2(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1:PWMHW\/cmp P6_3(0)_PAD 34.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,0) 1 \PWM_1:PWMHW\ \PWM_1:PWMHW\/clock \PWM_1:PWMHW\/cmp 1.000
Route 1 Net_187 \PWM_1:PWMHW\/cmp Net_43/main_1 7.413
macrocell3 U(0,1) 1 Net_43 Net_43/main_1 Net_43/q 3.350
Route 1 Net_43 Net_43/q P6_3(0)/pin_input 7.501
iocell14 P6[3] 1 P6_3(0) P6_3(0)/pin_input P6_3(0)/pad_out 15.011
Route 1 P6_3(0)_PAD P6_3(0)/pad_out P6_3(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1:PWMHW\/cmp P12_6(0)_PAD 28.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,0) 1 \PWM_1:PWMHW\ \PWM_1:PWMHW\/clock \PWM_1:PWMHW\/cmp 1.000
Route 1 Net_187 \PWM_1:PWMHW\/cmp P12_6(0)/pin_input 11.256
iocell8 P12[6] 1 P12_6(0) P12_6(0)/pin_input P12_6(0)/pad_out 16.220
Route 1 P12_6(0)_PAD P12_6(0)/pad_out P12_6(0)_PAD 0.000
Clock Clock path delay 0.000
+ PWM_2_Clock(fixed-function)
Source Destination Delay (ns)
\PWM_2:PWMHW\/cmp P6_3(0)_PAD 34.526
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,1) 1 \PWM_2:PWMHW\ \PWM_2:PWMHW\/clock \PWM_2:PWMHW\/cmp 1.000
Route 1 Net_186 \PWM_2:PWMHW\/cmp Net_43/main_0 7.664
macrocell3 U(0,1) 1 Net_43 Net_43/main_0 Net_43/q 3.350
Route 1 Net_43 Net_43/q P6_3(0)/pin_input 7.501
iocell14 P6[3] 1 P6_3(0) P6_3(0)/pin_input P6_3(0)/pad_out 15.011
Route 1 P6_3(0)_PAD P6_3(0)/pad_out P6_3(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_2:PWMHW\/cmp P6_2(0)_PAD 34.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,1) 1 \PWM_2:PWMHW\ \PWM_2:PWMHW\/clock \PWM_2:PWMHW\/cmp 1.000
Route 1 Net_186 \PWM_2:PWMHW\/cmp Net_50/main_0 6.761
macrocell4 U(0,2) 1 Net_50 Net_50/main_0 Net_50/q 3.350
Route 1 Net_50 Net_50/q P6_2(0)/pin_input 7.429
iocell13 P6[2] 1 P6_2(0) P6_2(0)/pin_input P6_2(0)/pad_out 15.746
Route 1 P6_2(0)_PAD P6_2(0)/pad_out P6_2(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_2:PWMHW\/cmp P12_7(0)_PAD 27.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,1) 1 \PWM_2:PWMHW\ \PWM_2:PWMHW\/clock \PWM_2:PWMHW\/cmp 1.000
Route 1 Net_186 \PWM_2:PWMHW\/cmp P12_7(0)/pin_input 9.934
iocell9 P12[7] 1 P12_7(0) P12_7(0)/pin_input P12_7(0)/pad_out 16.967
Route 1 P12_7(0)_PAD P12_7(0)/pad_out P12_7(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q P6_0(0)_PAD 29.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_6/main_0 2.302
macrocell6 U(0,2) 1 Net_6 Net_6/main_0 Net_6/q 3.350
Route 1 Net_6 Net_6/q P6_0(0)/pin_input 7.331
iocell11 P6[0] 1 P6_0(0) P6_0(0)/pin_input P6_0(0)/pad_out 14.914
Route 1 P6_0(0)_PAD P6_0(0)/pad_out P6_0(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 228.206 MHz 4.382 78.951
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 3.132
count7cell U(1,3) 1 \CapSense:ClockGen:ScanSpeed\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 4.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 3.132
count7cell U(1,3) 1 \CapSense:ClockGen:ScanSpeed\ REMOVAL 0.000
Clock Skew 0.000